1. Field of the Invention
The present invention relates to an image reading device that reads an image from an original document, an image processing apparatus including a memory for storing a read image, and a control method thereof.
2. Description of the Related Art
Existing image processing apparatuses provide functions for reading an image from an original document and storing the image in a memory or transmitting the image to another apparatus. With respect to such image processing apparatuses, a technique has been proposed in which work memory is shared in a main memory to reduce the amount of internal buffer and to reduce cost. In addition, the capacity of the main memory is reduced by compressing image data to be stored in the main memory. As shown, a generally-used method involves sharing a memory in order to reduce memory capacity required by the respective processing blocks and to reduce cost.
Image processing performed by a general image processing apparatus will now be described. With an image processing apparatus, image data input from a CCD (charge coupled device) that is an image reading device is subjected to A/D conversion and stored in a main memory. The image data stored in the main memory is subjected to image processing and JPEG compression, and subsequently, once again stored in the main memory. When using the data, only necessary data is read out from the main memory to be expanded and printed. Such write processing from the respective processing blocks to the main memory and read processing from the main memory is controlled by a DMAC (direct memory access controller).
Japanese Patent Laid-Open No. 2004-220585 proposes an image processing apparatus including a DMAC corresponding to image data to be input from an image reading device such as a CCD and which frame-sequentially stores the image data in different regions on the main memory. However, image compression/expansion processing (JPEG, JBIG, and the like) is performed on dot-sequential image data. In consideration thereof, the image processing apparatus according to Japanese Patent Laid-Open No. 2004-220585 improves image processing efficiency by reading image data frame-sequentially stored on the main memory, and after performing scanner image processing, storing the image data in an arrangement suitable for subsequent-stage image processing (dot sequential).
However, the conventional art described above has the following problem. Since the aforementioned image processing apparatus shares a main memory, a greater amount of data is transferred on a bus used by image processing, causing a decline in the overall performance of the system. In particular, a scanner I/F and a scanner image processing unit handle data per line and therefore require large memory regions. Consequently, a performance decline occurs such as becoming unable to accommodate a high-speed reading device.
A conceivable solution to the problem described above involves performing scanner image processing outside of a main control system that integrally controls an image processing apparatus for the purpose of accommodating a high-speed reading device. However, even if data after image processing is input via a scanner I/F, since the input data is to be stored frame-sequentially, a frame-sequential-to-dot-sequential conversion becomes necessary. Therefore, used memory cannot be reduced and the overall performance of the image processing apparatus cannot be improved. Furthermore, since data after scanner image processing sometimes includes image area data or the like in addition to image data, performing scanner image processing outside of the system also requires that transferring data other than image data be considered.